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PhD Oral Examination of Kapil Upamanyu @ 10 am on Thursday, May 11, 2023

May 11 @ 3:30 PM - 5:00 PM IST

PhD Oral Examination
Name of the candidate: Kapil Upamanyu
Programme:                     PhD (Regular)
Department:                    Electrical Engineering
Modelling, Stabilization Methods and Power Amplification for Power Hardware-in-Loop Simulation with Improved Accuracy
Supervisor:                       G Narayanan
Date:                                May 11, 2023 (Thursday)
Time:                                10 am – 11:30 am
Venue:                              Multi-Media Class Room (MMCR), EE Department (Hybrid mode)
Video link:                       Please find below:
All are welcome

Meeting link


Thesis title: Modelling, Stabilization Methods and Power Amplification for Power Hardware-in-Loop Simulation with Improved Accuracy


Simulations of physical systems are extensively conducted for research and design purpose. Potential of a simulation can be extended significantly by conducting it in real-time. Real-time simulation allows a part of the mathematical model of the system to be replaced by a physical hardware; the real-time simulator (RTS) and the physical hardware interact with each other through sensors and power amplifier (PA). When the operating power level of the PA is considerably higher than that of the sensor signals, the simulation is called as power hardware in loop (PHIL) simulation. PHIL simulation is a good alternative to the conventional simulation where a part of the system cannot be adequately represented by a mathematical model. Unlike conventional simulation, PHIL simulation allows the testing of a hardware, in a safe and controlled environment, without the rest of the system being available. But several factors, such as the computation time delay and sampling effects of RTS, the dynamics of PA and the transport lag of signals, are part of a PHIL simulation but not that of the actual system. As a result, the response of the PHIL simulation of a system can differ from that of the actual system. The inaccuracy can be so significant that the PHIL simulation of a system can be unstable even though the actual system is stable, and vice versa. An unstable PHIL simulation can be stabilized by employing compensation algorithms. This work proposes novel PA for accurate response, stability analysis methodology for the accurate estimation of instability, and compensation algorithms for stable response of PHIL simulation.

Conventional switched-mode PAs have limited dynamic response due the presence of passive filter. These PAs employed in a PHIL simulation are unable to accurately replicate the fast transients of the system. An output filter-less voltage source inverter is proposed as a power amplifier suitable to be interfaced with inductive loads (e.g., most of the power system loads). Such a PA has a reference tracking bandwidth comparable to the switching frequency. Unlike the output of the conventional PAs, the output of the proposed PA is completely unaffected by the sudden changes in the current drawn by the loads. The proposed PA is utilized to emulate the transients of synchronous generator, along with the fast transient corresponding to the field excitation controller, while feeding a passive linear load. With a proposed improvement in the emulation method, accurate responses for unbalanced and non-linear loads are also obtained for the emulated generator. With further proposed techniques, the applicability of the proposed PA is extended for it to be interfaced to PWM converters. The PA is utilized for emulating unbalanced and harmonic (up to 23rd order) grid voltages while testing the control of a PWM rectifier. Accurate current responses are also obtained when the step changes in the grid voltage and the rectifier dc bus reference are considered.

Conventionally, stability analysis of PHIL simulation is evaluated in continuous-time domain. Since, a PHIL simulation consists of discrete-time sampling, a discrete-time domain modelling approach is proposed for more accurate stability analysis. The proposed approach is also used to accurately estimate the stability of a PHIL simulation utilizing compensation algorithms, such as feedback current filtering method. Novel compensation algorithms, based on lag compensator and cross coupled compensator, are proposed for stabilizing those PHIL simulations which cannot be stabilized using existing algorithms. PHIL simulation of a single generator infinite bus power system, which is originally unstable without and with existing compensation algorithms, is successfully conducted using the novel cross-coupled compensator.

PA sourced from a PWM rectifier can be used as 4-quadrant PA. A simple input voltage sensor-less vector control of PWM rectifier is proposed. While the performance of the proposed method, in terms of THD and power factor, is comparable to the sensor-based method and existing sensor-less methods, its computation time requirement is much lower than those for these methods. A discrete-time domain modelling of the PI-controlled current loop of PWM converters is presented. The model is used to derive closed-form time-domain expressions of the current for step changes in the current reference and the disturbance voltage, for a given set of controller and hardware parameters. Based on the derived expressions, a pre-filter is proposed to achieve the dead-beat response with the PI-controlled current loop, while having a disturbance rejection settling time of just ten switching cycles.



May 11
3:30 PM - 5:00 PM IST


Multi-Media Class Room (MMCR), EE Department (Hybrid mode)