PhD Oral Exam

Title: Reduced Electrolytic Capacitor-Based Single-Phase Converters: Topologies, Control, and Stability

Name of the Student: Anwesha Mukhopadhyay
Name of the Advisor: Prof. Vinod John
Degree Registered: Ph.D.

Date and Time:  25th March, 2024, 08:00 AM

Teams Meeting Link:

Abstract: Single-phase power converters find wide applications as inverters. Applications ranging from a few hundred Watts for household solar micro-inverters, to multi-Megawatt levels for electric traction power train, single-phase converters are adopted worldwide.
In single-phase power conversion, there is always a mismatch between the instantaneous input and output power, producing a second-harmonic ripple in the dc link current. Electrolytic capacitors are conventionally deployed for filtering the second-harmonic ripple due to their low cost and excellent energy density. However, their frequent premature failures often compromise the lifespan of the converters. In recent technologies demanding high power density, active filters have minimised the electrolytic capacitors in the circuit. However, the cost, efficiency, and power density trade-offs need scrutiny before adopting an active filter topology.
Among the reported active filters (AF) for second-harmonic ripple mitigation, series capacitor stacked buffer (SSB) topology has emerged as a popular choice owing to its high efficiency and compactness. The use of low VA-rated switching devices enables achieving the high efficiency equivalent to passive filters. Despite its prospective utility in a range of applications, the model of the SSB, essential for implementing functional engineering control strategies under a wide range of operating conditions, is not discussed in existing literature.
In the first part of the work, the plant model for controlling the buffer converter in voltage control mode as well as current control mode is developed. Using the proposed model, a closed-loop control scheme is developed, which ensures a fixed-frequency switching of the buffer converter. A step-by-step controller design procedure is elaborated, and the controller gain limit is identified to ensure closed-loop stability.
Based on the developed SSB model, an average current mode control is implemented in the second part of the work. Unlike the existing methods of current mode control, in the proposed scheme, the current reference is estimated without using the dc-link current sensor, which is verified experimentally.
The SSB-based existing topologies, though promising for many applications, are not realised with minimum switch counts. As opposed to four switch H-bridge-based buffer converter, two switch-based series capacitor stacked buffer converter topologies are synthesised in this part of the work. The generalised topology synthesis procedure and control challenges are identified. One of the proposed two-switch-based topologies named Series Capacitor Boost Hybrid Filter (SC-BOHF) is implemented and verified experimentally.
Apart from the active solutions, an alternative dc bus filter structure, consisting of a combination of an inductor (L) and capacitor (C), tuned at the second harmonic (2ω) frequency, reduces the capacitance requirement, enhancing the likelihood of deployment of film capacitors. The proposed solid-state tuning restorer (SSTR) offers consistent filtering performance of the LC filter under frequency and parameter variations. As per the tuning requirement of the LC filter, SSTR acts as an electronic inductor or capacitor. It also ensures a graceful degradation in the filter characteristics during SSTR converter failure modes. The evolution of the SSTR configuration, analysis of its VA rating, and control requirements are studied in this work.
The realisation that SSTR requires to behave as an electronic inductor and capacitor as per the sense of LC filter detuning motivated this part of the work, where a unified active capacitor and inductor (UACI) is proposed and implemented without using any dc capacitor. Based on the current reference, the proposed configuration emulates inductive or capacitive characteristics and smoothly transits from one characteristic to another. The operation of the proposed UACI is studied, and a closed-loop control scheme is developed.
All the proposed methods are validated on hardware prototypes that have been developed as a part of the research.

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