PhD Thesis Colloquium on Solid-State Point-on-Wave Fault Creator with Adjustable Transient Recovery Voltage

Title: Solid-State Point-on-Wave Fault Creator with Adjustable Transient Recovery Voltage

Student: Rajesh K B

Faculty Advisor: Dr. Gurunath Gurrala.

Date : 18^th October 2024

Time: 11 AM – 12 PM

Venue: MMCR, EE, IISc, 1^st Floor

ABSTRACT:

The power grid is changing with the exponentially growing penetration of inverter-based resources (IBRs). Keeping the power grid stable, reliable, and secure, and delivering quality power has become increasingly important in recent years. As a result, many countries have devised grid codes for operating IBRs. Grid codes specify the requirements for IBRs to stay connected to the grid during various grid conditions, such as short circuit faults. As a result, a variety of devices are being developed to create grid short-circuit fault conditions. In addition to validating grid codes, devices capable of generating accurate and realistic fault transients are highly desirable for developing effective protection countermeasures, testing relay algorithms, studying fault characteristics in IBRs, and performing parameter estimation of power system components. Existing converter-based fault creators require high bandwidth control to provide an adjustable transient recovery voltage (TRV) feature. Providing this feature in the existing PWFCs utilizing FQSes is also difficult due to multiple over-voltage clamping circuits. The time series data generated during faults in power systems is essential for the development and validation of data-driven algorithms for power systems anomaly detection, classification, and mitigation.

This thesis explores the design of a point-on-wave fault creator (PWFC) with an adjustable transient recovery voltage feature. The developed PWFC can create all types of balanced and unbalanced faults at any desired angle on the voltage waveform (point-on-wave). Over-voltage protection is essential for solid-state switches in fault creators while clearing the fault. Existing fault creators using FQS, use one or two capacitors/surge protection devices per FQS for over-voltage protection. Hence fault creators with ‘N’ FQSes need ‘N’ or ‘2N’ capacitors, which increases the number of capacitors used in the fault creator, making it costly and bulky. In contrary to this, the PWFC topology in the author’s master thesis uses a single capacitor to protect all FQSes from overvoltage. A systematic analytical procedure to select the single capacitor value, adjustable transient recovery voltage feature, and a finite state machine (FSM) for PWFC control is developed in this thesis. The performance of the FQS and the PWFC are investigated under a wide range of test scenarios including thermal considerations and parasitic components. The ability of the selected capacitor to protect the FQSes during all types of fault clearances is experimentally validated by creating faults in an experimental test bed using the PWFC prototype. A novel FQS topology is proposed that can be realized using two commercially available half-bridge semiconductor modules. With this unique method of FQS realization, the lowest package count (Two), lowest on-state drop (one active switch plus one diode), modularity and scalability of the structure, gate control, and minimal package inter-connection length are simultaneously achieved. An adjustable TRV feature is achieved using a variable output voltage pre-charge circuit as a cost-effective solution. An algorithm is proposed to obtain the initial capacitor voltage required to limit the TRV to a specified target value. The experimental results demonstrated the ability of the PWFC to adjust the TRV for all fault configurations as per the test requirements.

A combined fault and power quality disturbance detection and classification method using symbolic dynamic filtering (SDF) is also developed. An SDF is constructed based on the symbolic encoding of time series data and finite state automata to generate steady-state probability distribution vectors (histograms) as signature patterns for different fault categories and power quality events.  It provides an edge over existing methodologies as it compresses voluminous fault data into fixed-length probability distributions, which serve as the feature vectors for classifiers. Irrespective of the length of the time series data or the number of coefficients of the transformation used, the feature vector’s length is fixed in SDF. A new sinusoidally distributed partitioning (SDP) scheme is proposed for symbolic encoding. The proposed methodology can detect and classify low-impedance faults, high-impedance faults, and power quality disturbances. Support vector machines and k-nearest neighbor classifiers are explored for fault classification using the histograms. The proposed methodology is tested on two active distribution systems, the modified IEEE 33 and 13 bus systems. In addition to fault detection and classification, a data-driven method is proposed to identify the hardware signature of Intelligent Electronic Devices (IED) used in power grids. It utilizes test function data of the analog-to-digital converter (ADC) used in the IED. A credit card-sized Parallella board and ADC of a custom IED platform are utilized to obtain the hardware signature. A finite state machine is developed in the FPGA of the Parallella processor to control the ADC for generating different data sets to extract signature 

Acknowledgments:

• Fund for Improvement of Science and Technology (FIST) Program, Department of Science and Technology (DST), India, through the project “Smart Energy Systems Infrastructure Hybrid Test Bed,” under Grant SR/FST/ETII-063/2015 (C) and (G)
• POWERGRID Center of Excellence in Cyber Security (PGCoE), IISc
• Department of Science and Technology, India, under the Indo-Danish collaboration project, Data-Driven Control and Optimization for a Highly Efficient Distribution Grid (ID-EDGE), No. DST-1390-EED