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X-WR-CALDESC:Events for EE
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TZID:Asia/Kolkata
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DTSTART:20240101T000000
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241014T110000
DTEND;TZID=Asia/Kolkata:20241014T120000
DTSTAMP:20260526T183448
CREATED:20241011T071537Z
LAST-MODIFIED:20241015T104930Z
UID:241796-1728903600-1728907200@ee.iisc.ac.in
SUMMARY:PhD Thesis Colloquium
DESCRIPTION:Title: Parallel Algorithms for Efficient Utilization of Multiprocessor Architectures for Transient Stability \nStudent: Francis C Joseph \nFaculty Advisor: Dr. Gurunath Gurrala. \nDate :14th October 2024 \nTime: 11 AM – 12 PM \nONLINE TEAMS LINK \nABSTRACT: \nComputer hardware capabilities have been enormously increasing over the years. Multi-core processors\, graphic processing units (GPUs)\, and field programmable gate array (FPGA) accelerators have grown significantly recently. They have opened new computational paradigms such as edge computing\, fog computing\, grid computing\, distributed computing\, cloud computing\, and exascale supercomputing. However\, efficiently utilising most of these computational paradigms in traditional engineering disciplines\, such as power engineering\, is challenging. In this thesis\, efficient algorithms for multiprocessor-based high-performance computing and edge computing platforms for two power system applications are developed\, power system stability assessment and power quality measurements respectively. Faster than real-time transient stability assessment of large power grids using time domain simulations with detailed models is computationally challenging. Today\, the commercial tools used for this application in Energy Management Systems (EMS) worldwide rely on parallel batch processing methods\, which don’t efficiently utilise the architecture of the computational paradigms. For transient stability simulations\, this thesis explores a time parallel algorithm\, Parareal in Time\, which belongs to a class of temporal decomposition methods for time parallel solutions of differential equations. Two effective implementation approaches\, Master Worker and Distributed\, are analysed for large systems\, and scaling tests are performed using a state space model with a Message Passing Interface (MPI) in a multiprocessor environment. One of the findings was that the performance of the Parareal depends on the accuracy and the computational cost of the coarse solver used for initialisation and subsequent correction steps. A potential coarse solver\, Modified Euler (ME)\, a well-known solver for transient stability simulations even in commercial packages\, has been explored to adapt its step size by controlling the Local Truncation Error (LTE) to achieve the desired accuracy. An LTE estimator using a Multistage Homotopy Analysis Method (MHAM)\, which gives an approximate solution to a set of non-linear equations in the form of a power series\, is proposed to control the LTE at each integration step to enable adaptation of the ME step size. The proposed MHAM-assisted adaptive ME solver is faster and has comparable accuracy to the conventional fixed and adaptive Modified Euler solver for large systems’ transient stability simulations. Since MHAM is lighter than the ME solver and the LTE estimate is sufficient for step size adaptation\, an adaptive MHAM coarse solver is proposed for the Parareal. However\, MHAM provides a non-zero auxiliary parameter `c’ to select a family of solutions. Hence\, an optimisation framework is also proposed to automatically select this parameter based on the system’s dynamics. Based on many case studies on test systems of different sizes\, it is found that maintaining the LTE lower than the Parareal convergence tolerance improves the speedup of the Master-Worker paradigm; however\, for the distributed implementation\, maintaining LTE higher than the convergence tolerance gives improved speedup. An approach to include unscheduled events which arise in power system operation due to the operation of protective relays is also proposed for Parareal. The impact of frequency estimation on Parareal is evaluated using three estimation methods. It was found that the network admittance-based method has the lowest execution time. Many different types of disturbance types are performed on systems of different sizes and see that Parareal can maintain its performance. In Parareal implementation\, each coarse time segment is assigned to one processor in the MPI environment. Multiple processors in a node can be assigned to a coarse time segment to improve speedup. Therefore\, a shared memory-based space parallel transient stability solver is also considered for further performance enhancement. Space parallelisation of transient stability simulation involves breaking the network into subnetworks and solving each part independently while ensuring the original network’s convergence. Therefore\, a Multi Area Thevenin Equivalent (MATE) based parallel solver implementation on a shared memory platform is proposed\, and both space parallelisation and task parallelisation are explored. It is shown that the space parallelism can closely match the ideal speedup and can be exceeded by space + task parallelism while the network is well-partitioned. It can be further improved when combined with time parallelism. A hybrid time-space solver using OpenMP MATE\, space + task parallelism\, and MPI Parareal is proposed using two scheduling schemes: homogeneous and heterogeneous for both communication paradigms. The homogeneous scheduling enabled a faster-than-real time solution even for the PEGASE 13659 bus system and provided multiple combinations to achieve it. The heterogeneous can increase the performance of the hybrid solver when homogeneous scheduling is unavailable. A particular case for Hybrid Master with a single core worker was used to showcase the initialisation phase’s time reduction by reducing the coarse solver’s computational time. The current state-of-the-art chips also provide multicore architectures for edge computing applications. One such low-cost\, open-source\, heterogeneous\, resource-constrained hardware platform is called Parallella. The unique hardware architecture of the Parallella provides many edge computing resources in the form of a Zynq SoC (dual-core ARM + FPGA) and a 16-core co-processor called Epiphany. This Parallella device was used as a measurement device for edge computing applications research in smart grids\, and it could sample 3 voltages and four currents at a 32 kHz sampling rate. The thesis explores one application of such a device to measure the harmonics and compute various Power Quality (PQ) indices. A parallel implementation of multichannel FFT on Epiphany for the streaming data is developed in this regard. Epiphany 16-core architecture has very limited memory resources\, and the order in which the cores are to be accessed significantly impacts the execution. Proper decomposition of the FFT algorithm tasks and scheduling the tasks for efficient core and memory usage are crucial\, requiring a good understanding of the Epiphany architecture. The obtained PQ measurements from the proposed implementation are comparable to those of a commercial power analyser. \n  \nAcknowledgments: \n\nSERB Science and Technology Award for Research (SERB-STAR) grant\, File No: STR/2020/000019 titled Hybrid Parallel Solvers for Faster than Real-time Transient Stability Analysis of Large Power Grids.\n\n\nBosch Research and Technology Centre\, Bangalore\, India and by the Robert Bosch Centre for Cyber-Physical Systems\, Indian Institute of Science\, Bangalore\, India (under Project E-Sense: Sensing and Analytics for Energy Aware Smart Campus)\nDST Young Scientist Grant DST-YSS/2015/001371\, India
URL:https://ee.iisc.ac.in/event/phd-thesis-colloquium-3/
LOCATION:Online\, India
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241018T110000
DTEND;TZID=Asia/Kolkata:20241018T120000
DTSTAMP:20260526T183448
CREATED:20241015T105102Z
LAST-MODIFIED:20241015T105310Z
UID:241798-1729249200-1729252800@ee.iisc.ac.in
SUMMARY:PhD Thesis Colloquium on Solid-State Point-on-Wave Fault Creator with Adjustable Transient Recovery Voltage
DESCRIPTION:Title: Solid-State Point-on-Wave Fault Creator with Adjustable Transient Recovery Voltage \nStudent: Rajesh K B \nFaculty Advisor: Dr. Gurunath Gurrala. \nDate : 18th October 2024 \nTime: 11 AM – 12 PM \nVenue: MMCR\, EE\, IISc\, 1st Floor \nABSTRACT: \nThe power grid is changing with the exponentially growing penetration of inverter-based resources (IBRs). Keeping the power grid stable\, reliable\, and secure\, and delivering quality power has become increasingly important in recent years. As a result\, many countries have devised grid codes for operating IBRs. Grid codes specify the requirements for IBRs to stay connected to the grid during various grid conditions\, such as short circuit faults. As a result\, a variety of devices are being developed to create grid short-circuit fault conditions. In addition to validating grid codes\, devices capable of generating accurate and realistic fault transients are highly desirable for developing effective protection countermeasures\, testing relay algorithms\, studying fault characteristics in IBRs\, and performing parameter estimation of power system components. Existing converter-based fault creators require high bandwidth control to provide an adjustable transient recovery voltage (TRV) feature. Providing this feature in the existing PWFCs utilizing FQSes is also difficult due to multiple over-voltage clamping circuits. The time series data generated during faults in power systems is essential for the development and validation of data-driven algorithms for power systems anomaly detection\, classification\, and mitigation. \nThis thesis explores the design of a point-on-wave fault creator (PWFC) with an adjustable transient recovery voltage feature. The developed PWFC can create all types of balanced and unbalanced faults at any desired angle on the voltage waveform (point-on-wave). Over-voltage protection is essential for solid-state switches in fault creators while clearing the fault. Existing fault creators using FQS\, use one or two capacitors/surge protection devices per FQS for over-voltage protection. Hence fault creators with ‘N’ FQSes need ‘N’ or ‘2N’ capacitors\, which increases the number of capacitors used in the fault creator\, making it costly and bulky. In contrary to this\, the PWFC topology in the author’s master thesis uses a single capacitor to protect all FQSes from overvoltage. A systematic analytical procedure to select the single capacitor value\, adjustable transient recovery voltage feature\, and a finite state machine (FSM) for PWFC control is developed in this thesis. The performance of the FQS and the PWFC are investigated under a wide range of test scenarios including thermal considerations and parasitic components. The ability of the selected capacitor to protect the FQSes during all types of fault clearances is experimentally validated by creating faults in an experimental test bed using the PWFC prototype. A novel FQS topology is proposed that can be realized using two commercially available half-bridge semiconductor modules. With this unique method of FQS realization\, the lowest package count (Two)\, lowest on-state drop (one active switch plus one diode)\, modularity and scalability of the structure\, gate control\, and minimal package inter-connection length are simultaneously achieved. An adjustable TRV feature is achieved using a variable output voltage pre-charge circuit as a cost-effective solution. An algorithm is proposed to obtain the initial capacitor voltage required to limit the TRV to a specified target value. The experimental results demonstrated the ability of the PWFC to adjust the TRV for all fault configurations as per the test requirements. \nA combined fault and power quality disturbance detection and classification method using symbolic dynamic filtering (SDF) is also developed. An SDF is constructed based on the symbolic encoding of time series data and finite state automata to generate steady-state probability distribution vectors (histograms) as signature patterns for different fault categories and power quality events.  It provides an edge over existing methodologies as it compresses voluminous fault data into fixed-length probability distributions\, which serve as the feature vectors for classifiers. Irrespective of the length of the time series data or the number of coefficients of the transformation used\, the feature vector’s length is fixed in SDF. A new sinusoidally distributed partitioning (SDP) scheme is proposed for symbolic encoding. The proposed methodology can detect and classify low-impedance faults\, high-impedance faults\, and power quality disturbances. Support vector machines and k-nearest neighbor classifiers are explored for fault classification using the histograms. The proposed methodology is tested on two active distribution systems\, the modified IEEE 33 and 13 bus systems. In addition to fault detection and classification\, a data-driven method is proposed to identify the hardware signature of Intelligent Electronic Devices (IED) used in power grids. It utilizes test function data of the analog-to-digital converter (ADC) used in the IED. A credit card-sized Parallella board and ADC of a custom IED platform are utilized to obtain the hardware signature. A finite state machine is developed in the FPGA of the Parallella processor to control the ADC for generating different data sets to extract signature  \nAcknowledgments: \n\nFund for Improvement of Science and Technology (FIST) Program\, Department of Science and Technology (DST)\, India\, through the project “Smart Energy Systems Infrastructure Hybrid Test Bed\,” under Grant SR/FST/ETII-063/2015 (C) and (G)\nPOWERGRID Center of Excellence in Cyber Security (PGCoE)\, IISc\nDepartment of Science and Technology\, India\, under the Indo-Danish collaboration project\, Data-Driven Control and Optimization for a Highly Efficient Distribution Grid (ID-EDGE)\, No. DST-1390-EED
URL:https://ee.iisc.ac.in/event/phd-thesis-colloquium-on-solid-state-point-on-wave-fault-creator-with-adjustable-transient-recovery-voltage/
LOCATION:MMCR\, Hall C 241\, 1st floor\, EE department
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241018T160000
DTEND;TZID=Asia/Kolkata:20241018T173000
DTSTAMP:20260526T183448
CREATED:20241007T043703Z
LAST-MODIFIED:20241015T112448Z
UID:241792-1729267200-1729272600@ee.iisc.ac.in
SUMMARY:Faculty Colloquium: Demystifying Large Language Models - Capabilities\, Challenges and Opportunities
DESCRIPTION:Title: Demystifying Large Language Models – Capabilities\, Challenges and Opportunities \nSpeaker: Dr. Sriram Ganapathy\, Associate Professor\, Dept of Electrical Engineering\, Indian Institute of Science \nVenue: MMCR\, EE \nTeam Link \nTime: 4pm\, 18 Oct 2024 \nAbstract:\nIn the last two years\, large language models (LLMs) have taken giant leaps in tackling real world problems ranging from reasoning\, coding\, creative content generation and multimodal understanding. This has resulted in significant user growths in services like chatGPT and Gemini. In this talk\, I will give a brief overview of i) what goes under the hood in developing these models\, ii) what their current capabilities are\, iii) who are the big players and iv) what are the potential challenges and blindspots. Along the way\, I will also touch upon some of the theory that allows basic understanding of how the LLMs achieve their capabilities. The talk will end with a discussion of bias\, safety and regulatory considerations in the development and deployment of these models. \nSpeaker’s Bio:\nSriram Ganapathy is an Associate Professor at the Electrical Engineering\, Indian Institute of Science\, Bangalore\, where he leads the activities of the Learning and Extraction of Acoustic Patterns (LEAP) lab. He is also a visiting research scientist at Google Research India\, Bangalore.  Prior to joining the Indian Institute of Science\, he was\na research staff member at the IBM Watson Research Center\, Yorktown Heights\, USA. He received his Doctor of Philosophy from the Center for Language and Speech Processing\, Johns Hopkins University. He obtained\nhis Bachelor of Technology from College of Engineering\, Trivandrum\, India and Master of Engineering from the Indian Institute of Science\, Bangalore.  He has also worked as a Research Assistant in Idiap Research\nInstitute\, Switzerland.  Dr. Ganapathy currently serves as the IEEE Sigport Chief Editor\, member of the IEEE Education Board\, and functions as subject editor for Elsevier Speech Communication Journal. He is also a recipient of multiple awards including Department of Science and Technology (DST) Early Career Award in India\, Department of Atomic Energy (DAE)\, India Young Scientist Award and Verisk AI Faculty Award.
URL:https://ee.iisc.ac.in/event/faculty-colloquium-demystifying-large-language-models-capabilities-challenges-and-opportunities/
LOCATION:EE\, MMCR
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241028T110000
DTEND;TZID=Asia/Kolkata:20241028T130000
DTSTAMP:20260526T183448
CREATED:20241028T051939Z
LAST-MODIFIED:20241028T051939Z
UID:241802-1730113200-1730120400@ee.iisc.ac.in
SUMMARY:Ph.D. Thesis Colloquium
DESCRIPTION:PhD Thesis Colloquium \nName of the Candidate: Kalla Jayateja\nResearch Supervisor: Soma Biswas\nDate and Time: October 28\, 2024\, Monday\, 11:00 AM\nVenue: C-241\, First Floor\, Multimedia Classroom (MMCR)\, EE \nTitle: Class Incremental Learning Across Diverse Data Paradigms \nAbstract: In recent years\, deep learning has achieved remarkable success in various domains\, largely due to its ability to learn from vast amounts of data. However\, traditional deep learning models struggle in scenarios where new classes are introduced over time\, requiring retraining from scratch or facing catastrophic forgetting of previously learned information. This limitation underscores the need for class incremental learning (CIL)\, a continual learning paradigm that enables models to adapt incrementally to new classes without losing prior knowledge. CIL is crucial in real-world scenarios\, such as autonomous driving and healthcare diagnostics\, where new data emerges continuously. Traditional CIL approaches often rely on idealized assumptions of balanced\, fully labeled\, and abundant datasets\, which rarely hold true in practice. In reality\, CIL models must handle dynamic environments like class imbalance\, limited supervision\, and data scarcity. This thesis tackles these issues by proposing novel methods tailored to diverse CIL scenarios\, emphasizing flexibility and robustness. We now describe the various CIL scenarios studied as part of this thesis. \nFirstly\, we introduce the Generalized Semi-Supervised Class Incremental Learning (GSS-CIL) protocol\, designed for scenarios with limited labeled data and abundant unlabeled data. In semi-supervised learning\, the quality of pseudo-labels plays a critical role. To address this challenge within the CIL framework\, we propose the Expert Suggested Pseudo-Labelling Network (ESPN)\, which utilizes an expert model to generate high-quality pseudo-labels from the unlabeled data at each incremental step\, ensuring a more robust learning process. \nIn many practical applications\, the number of samples per class can vary significantly\, leading to long-tailed distributions where a few classes are well-represented\, while most others are under-represented. This motivates the need for addressing long-tailed learning in CIL which stems from the inherent imbalance in real-world data distributions. We address this problem through a two-stage framework called Global Variance-Driven Classifier Alignment (GVAlign)\, where the first stage involves learning robust feature representations using Mixup loss. In the second stage\, the classifiers are aligned by leveraging global variance with class prototypes\, enabling learning robust representations even for under-represented classes. GVAlign can be seamlessly integrated into existing CIL approaches to effectively handle the long tailed data distributions. \nIn the next part\, we address the Few-Shot Class Incremental Learning (FSCIL) scenario\, where there are only a handful of examples available for each class. We address the two key challenges of FSCIL\, namely overfitting and catastrophic forgetting\, through the proposed method\, Self-Supervised Stochastic Classifier (S3C). In order to learn robust feature representations in the limited data regime and prevent overfitting\, we leverage self-supervised objectives. Specifically\, we train the feature extractor for the rotation prediction task. We observe that the network learnt in a self-supervised manner mitigates catastrophic forgetting in the incremental stages. We also propose to replace the conventional deterministic classifiers with stochastic classifiers\, where classifiers are sampled from a learnable distribution. This further aids the model in generalizing better to new classes and mitigates overfitting\, thereby improving performance in FSCIL scenarios. \nIn addition to addressing these specific CIL scenarios\, this thesis also focuses on the development of generalized methods that are adaptable across the variety of CIL scenarios and the amount of data supervision. Given the diversity inherent in incremental learning\, a single method may not suffice for all scenarios. We demonstrate that a straightforward self-supervision strategy can significantly enhance performance across multiple CIL tasks\, enabling our models to remain adaptable without the need for task-specific modifications. This approach\, being modular in nature\, can be seamlessly integrated with new techniques as they emerge. \nIn the final part of this thesis\, we propose a unified approach to address CIL across varying levels of supervision\, from few-shot to high-shot settings. By harnessing the rich representational capabilities of large-scale pre-trained models\, our method effectively handles the challenges posed by differing levels of supervision\, ensuring robust performance in both low-shot and high-shot CIL scenarios.
URL:https://ee.iisc.ac.in/event/ph-d-thesis-colloquium-4/
LOCATION:MMCR\, Hall C 241\, 1st floor\, EE department
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20241029T153000
DTEND;TZID=Asia/Kolkata:20241029T173000
DTSTAMP:20260526T183448
CREATED:20241029T064808Z
LAST-MODIFIED:20241029T064912Z
UID:241808-1730215800-1730223000@ee.iisc.ac.in
SUMMARY:[Talk] 7 Nov\, 3:30 PM\, Dr. Soham Chakraborty\, NREL\, USA
DESCRIPTION:Title:  Design of a Robust Power Hardware-in-the-Loop Interface Controller and an Enhanced Droop Control for Seamless Transfer \nSpeaker: \nDr. Soham Chakraborty \nPostdoctoral Researcher\nEnergy Systems Integration Facility\,\nNational Renewable Energy Laboratory\,\nGolden\, Colorado\, USA 80401\nDate: 7th November 2024\, 3:30 PM \nVenue: C 241\, MMCR\, EE Dept\, IISc \nAbstract: \n\nIn the first part of the talk\, the challenges of synthesizing an interface between the hardware and software components of PHIL will be discussed and talked about from a modern control perspective for managing inherent uncertainties. The proposed robust PHIL interface controller based on mu-synthesis ensures multiple objectives that includes robust stability\, performance\, accuracy\, and tracking capabilities. To assess the effectiveness and viability\, a PHIL experiment is conducted that involves interfacing an emulated software system based on a 1-φ\, 225-bus\, 110V\, 60Hz\, 1MW residential sub-network of the University of Minnesota and suburban Minneapolis interfaced with multiple hardware under tests. \nIn the second part of the talk\, a seamless transition strategy using a single and unified mode-dependent droop-controlled grid-forming inverters will be discussed. Seamless recovery of power to critical infrastructures\, after grid failure\, is a crucial need arising in scenarios that are increasingly becoming more frequent. The proposed control strategy regulates the output active and reactive power by the inverters to a desired value while operating in on-grid mode; seamless transition and recovery of power injections into the load after grid failure by inverters that operates in grid-forming mode all the time; and requires only a single bit of information on the grid/network status for the mode transition. A hardware experiment is conducted with two 3-φ\, 480-V\, 125-kVA grid-forming inverters\, a 3-φ\, 480-V\, 270-kVA grid simulator\, a physical grid switch\, and a physical load bank.\n\n Short Biography:\nSoham Chakraborty received the B.E. degree from Bengal Engineering and Science University\, Shibpur\, India\, in 2013\, the M.Tech. degree from the\nIndian Institute of Technology\, Mumbai\, India\, in 2016\, and the PhD degree from the  the University of Minnesota\, Minneapolis\, MN\, USA in 2023; all in electrical engineering. The title of his PhD thesis was “Robust Dynamic Resilient Power Grids Enabled By Modern Control Framework”.\nHe is currently working as a Post-Doctoral Fellow at the Energy Systems Integration Facility\, National Renewable Energy Laboratory\, USA from 2023.
URL:https://ee.iisc.ac.in/event/talk-7-nov-330-pm-dr-soham-chakraborty-nrel-usa/
LOCATION:MMCR\, Hall C 241\, 1st floor\, EE department
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