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DTSTART;TZID=Asia/Kolkata:20230728T160000
DTEND;TZID=Asia/Kolkata:20230728T173000
DTSTAMP:20260528T153652
CREATED:20230727T063239Z
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SUMMARY:EE PhD Thesis Colloquium -- Francis C Joseph -- 28th July\, 4 PM
DESCRIPTION:Title: Parallel Algorithms for Efficient Utilization of Multiprocessor Architectures in Power System ApplicationsSpeaker: FRANCIS C JOSEPH . of Ph.D. (Engg) in Electrical Engineering under Electrical EngineeringDate/Time: Jul 28 / 16:00:00Location: Room 303\, 2nd Floor\, EEResearch Supervisor: Dr. Gurunath GurralaAbstract:Computer hardware capabilities have been enormously increasing over the years. Multi-core processors\, graphic processing units (GPUs)\, and field programmable gate array (FPGA) accelerators have seen significant growth in recent years. They have opened new computational paradigms such as edge computing\, fog computing\, grid computing\, distributed computing\, cloud computing\, and exascale supercomputing. However\, efficient utilization of most of these computational paradigms in traditional engineering disciplines such as power engineering is very challenging. In this thesis\, we develop efficient algorithms for multiprocessor-based high-performance computing and edge computing platforms for two power system applications\, power system stability assessment and power quality measurements respectively.Faster than real-time transient stability assessment of large power grids using time-domain simulations with detailed models is comp utationally challenging. Today the commercial tools being used for this application in Energy Management Systems (EMS) across the world rely on parallel batch processing methods which don’t utilize the architecture of the computational paradigms efficiently. In this thesis for transient stability simulations\, we explore a time parallel algorithm\, Parareal in Time\, which belongs to a class of temporal decomposition methods for time parallel solutions of differential equations. Two effective implementation approaches\, Master Worker and Distributed\, are analysed for large systems\, and scaling tests are performed using a state space model with a Message Passing Interface (MPI) in a multiprocessor environment. One of the findings was that the performance of the Parareal depends on the accuracy and the computational cost of the coarse solver used for initialization and subsequent correction steps. A potential coarse solver\, Modified Euler (ME)\, a well-known solver for transient stability simulations even in commercial packages\, has been explored to adapt its step size by controlling the Local Truncation Error (LTE) to achieve the desired accuracy. An LTE estimator using a Multistage Homotopy Analysis Method (MHAM)\, which gives an approximate solution to a set of non-linear equations in the form of a power series\, is proposed to control the LTE at each integration step to enable adaptation of the ME step size. The proposed MHAM-assisted adaptive ME solver is found to be faster with comparable accuracy when compared to the conventional fixed and adaptive Modified Euler solver for large systems transient stability simulations. Since MHAM is lighter than the ME solver and LTE estimate is sufficient for step size adaptation\, an adaptive MHAM coarse solver is proposed for the Parareal. However\, MHAM provides a non-zero auxiliary parameter `c’ to select a family of solutions. Hence\, an optimisation framework is also proposed to select this parameter based on the system’s dynamics automatically. Based on many case studies on test systems of different sizes\, it is found that maintaining the LTE lower than the Parareal convergence tolerance improves the speedup of the Master-Worker paradigm\, however for the distributed implementation maintaining LTE higher than the convergence tolerance gives improved speedup. An approach to include unscheduled events which arise in power system operation due to the operation of protective relays is also proposed for Parareal.In Parareal implementation\, each coarse time segment is assigned to one processor in the MPI environment. In order to improve speedup\, multiple processors in a node is to be assigned to a coarse time segment. Therefore\, a shared memory-based space parallel transient stability solver is also considered for further performance enhancement. Space parallelisation of transient stability simulation involves breaking the network into subnetworks and solving each part independently while ensuring the original network’s convergence. Therefore\, a Multi Area Thevenin Equivalent (MATE) based parallel solver implementation on a shared memory platform is proposed in which both the space parallelisation and task parallelisation are explored. It is shown that the ideal speedup can be closely matched by the space parallelism and can be exceeded by space + task parallelism while the network is well-partitioned and it can be further improved when combined with time parallelism. The current state-of-the-art chips provide multicore architectures for edge computing applications also. One such low-cost\, open-source\, heterogeneous\, resource-constrained hardware platform is called “Parallella”. The unique hardware architecture of the Parallella provides many edge computing resources in the form of a Zynq SoC (dual-core ARM + FPGA) and a 16-core co-processor called Epiphany. This Parallella device was used as a measurement device for edge computing applications research in smart grids which could sample 3 voltages and 4 currents at 32 kHz sampling rate. One application of such a device to measure the harmonics and compute various Power Quality (PQ) indices is explored in the thesis. In this regard\, we have developed a parallel implementation of multichannel FFT on Epiphany for the streaming data. Epiphany 16-core architecture has very limited memory resources and the order in which the cores are to be accessed has a significant impact on the execution. Proper decomposition of the FFT algorithm tasks and scheduling of the tasks for efficient core and memory usage are crucial which requires a good understanding of the Epiphany architecture. The obtained PQ measurements from the proposed implementation are found to be comparable to commercial power analyser measurements.Acknowledgements: This work is funded by the • SERB Science and Technology Award for Research (SERB-STAR) grant\, File No: STR/2020/000019 titled Hybrid Parallel Solvers for Faster than Real-time Transient Stability Analysis of Large Power Grids. • Bosch Research and Technology Centre\, Bangalore\, India and by the Robert Bosch Centre for Cyber-Physical Systems\, Indian Institute of Science\, Bangalore\, India (under Project E-Sense: Sensing and Analytics for Energy Aware Smart Campus) • DST Young Scientist Grant DST-YSS/2015/001371\, IndiaMeeting Link : \n\n\n\n\n\n\n\n\nJoin conversation\nteams.microsoft.com
URL:https://ee.iisc.ac.in/event/ee-phd-thesis-colloquium-francis-c-joseph-28th-july-4-pm/
LOCATION:B 303 (Old 311)\, Dept. of Electrical Engineering (Hybrid Mode)
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DTSTART;TZID=Asia/Kolkata:20230728T163000
DTEND;TZID=Asia/Kolkata:20230728T173000
DTSTAMP:20260528T153652
CREATED:20230725T041910Z
LAST-MODIFIED:20230725T041950Z
UID:240904-1690561800-1690565400@ee.iisc.ac.in
SUMMARY:[Thesis Defense Talk - Shreyas Ramoji\, 28/7 @430pm\, MMCR\, EE] - "Supervised Learning Approaches for Language and Speaker Recognition"
DESCRIPTION:Thesis Defense Talk\n \nVenue: MMCR\, EE\nDate: 28/7/2023\nTime: 4:30pm [High Tea at 4:15pm]\nSpeaker: Shreyas Ramoji\n\nTitle: Supervised Learning Approaches for Language and Speaker Recognition\n\n\nAbstract:\nIn the age of artificial intelligence\, one of the important goals of the speech processing research community is to enable machines to automatically recognize who is speaking and in what language.\n\nIn the first part of this talk\, I will discuss our efforts towards a supervised version of the generative model based embedding extractor for speaker and language recognition. We call the embeddings from this supervised approach as s-vectors. In this approach\, a database of speech recordings (in the form of a sequence of short-term feature vectors) is modeled with a Gaussian Mixture Model\, called the Universal Background Model (GMM-UBM). The deviation in the mean components is captured in a lower dimensional latent space\, called the i-vector space\, using a factor analysis framework. In our research\, we propose a fully supervised version of the i-vector model\, where each label class is associated with a Gaussian prior with a class-specific mean parameter. The joint prior (marginalized over the sample space of classes) on the latent variable becomes a GMM. With detailed data analysis and visualization\, we show that the s-vector features yield representations that succinctly capture the language (accent) label information and also perform significantly improved the recognition of various accents of the same language.\n\nIn the second part of the talk\, I will discuss our efforts for the problem of fully supervised end-to-end speaker verification\, where a binary decision has to be made whether a pair of recordings belong to the same speaker or not. We proposed a neural network approach for back-end modeling\, where the likelihood ratio score of the generative probabilistic discriminative analysis (PLDA) model is posed as a discriminative similarity function\, and the learnable parameters of the score function are optimized using a verification cost. The proposed model\, termed as neural PLDA (NPLDA)\, is initialized using the generative PLDA model parameters. The loss function for the NPLDA model is an approximation of the minimum detection cost function (DCF) used as one of the evaluation metrics in various speaker verification challenges. The speaker recognition experiments using the NPLDA model are performed on the speaker verification task in the VOiCES datasets as well as the SITW challenge dataset. Further\, we explore a fully neural approach where the neural model outputs the verification score directly\, given the acoustic feature inputs. This Siamese neural network (E2E-NPLDA) model combines embedding extraction and back-end modeling into a single processing pipeline. Several speaker recognition experiments were performed on benchmark datasets where the proposed N  E2E-NPLDA models are shown to improve significantly over the then state-of-art system.\n\nI will conclude the talk by highlighting some of the noteworthy approaches that were published during the course of this research work\, and identifying some important research directions related to this thesis that can be pursued in the future.\n\nBio:\nShreyas Ramoji is a Research Associate at the Learning and Extraction of Acoustic Patterns (LEAP) Laboratory\, Department of Electrical Engineering\, Indian Institute of Science\, Bengaluru. He obtained his Bachelor of Engineering degree from the Department of Electronics and Communication Engineering\, PES Institute of Technology\, Bangalore South Campus. His research interests include speaker and language recognition\, diarization\, representation learning for multilingual and conversational speech\, ML/AI applied to healthcare and the environment\, natural language processing\, explainability and interpretability of neural networks\, and neuro-symbolic AI.\n\n\n\n\n\n—
URL:https://ee.iisc.ac.in/event/thesis-defense-talk-shreyas-ramoji-28-7-430pm-mmcr-ee-supervised-learning-approaches-for-language-and-speaker-recognition/
LOCATION:MMCR\, Hall C 241\, 1st floor\, EE department
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